The present invention relates to a self-bias adjustment circuit, arranged on a previous stage of an internal circuit, for supplying an appropriate signal to an internal circuit.
As a conventional self-bias adjustment circuit, for example, a self-bias adjustment circuit disclosed in a reference xe2x80x9cDesign Considerations for Very-High-Speed Si-Bipolar IC""s Operating up to 50 Gb/sxe2x80x9d, H.-M. rein (IEEE Journal of Solid-State Circuits, vol. 31, no. 8, pp. 1076-1090, August 1996). FIG. 6 is a schematic diagram showing the configuration of an integrated circuit including the conventional self-bias adjustment circuit. This integrated circuit 82 comprises an input terminal 87 which receives a signal current I80 from an output circuit 84 of another integrated circuit 81 through a signal transmission line 86, a terminal resistor 88 (resistance RS80) arranged between a high-potential side 82a of the power supply of the integrated circuit 82 and the input terminal 87, and an internal circuit 89.
A potential difference VGAP80 is generated across the low-potential side 81b of the power supply of the other integrated circuit 81 and a low-potential side 82b of the power supply of the integrated circuit 82. The output circuit 84 of the other integrated circuit 81 has a signal current source 85 to output the signal current 180 from the signal current source 85 to the signal transmission line 86. The terminal resistor 88 constitutes a self-bias adjustment circuit 91. The power supply voltage of the integrated circuit 81 and the power supply voltage of the integrated circuit 82 are equal to each other. More specifically, equation (1) is established:
(VCC81xe2x88x92VEE81)=(VCC82xe2x88x92VEE82)xe2x80x83xe2x80x83(1) 
In this equation, VCC81 denotes the voltage of a high-potential voltage side 81a of the power supply of the integrated circuit 81, VEE81 denotes the voltage of the low-potential side 81b of the power supply of the integrated circuit 81, VCC82 denotes the voltage of the high-potential side 82a of the power supply of the integrated circuit 82, and VEE82 denotes the voltage of the low-potential side 82b of the power supply of the integrated circuit 82. The internal circuit 89 may be an internal circuit having a single-phase output or an internal circuit having a differential output. The output impedance of the output circuit 84 is equal to the impedance of the signal transmission line 86. The impedance of the terminal resistor 88 is equal to the impedance of the signal transmission line 86. The internal circuit 89 has a high-input impedance of several kxcexa9 or more.
The signal current I80 output from the output circuit 84 is flowed into the high-potential side 82a of the power supply of the integrated circuit 82 through the input terminal 87 and the terminal resistor 88. If a potential difference VGAP80 is 0 volt, a DC voltage VDC80 across the input terminal 87 and an input terminal 90 can be expressed by equation (2). A signal amplitude (amplitude of signal voltage) VAC80 between the input terminals 87 and 90 can be expressed by equation (3).
VDC80=VCC82xe2x88x92(I80xc3x97RS80)/2xe2x80x83xe2x80x83(2) 
VAC80=I80xc3x97RS80xe2x80x83xe2x80x83(3) 
When bias design for the internal circuit 89 is performed in accordance with signal voltages expressed by equation (2) and equation (3), the internal circuit 89 can be normally operated. In this manner, a self-bias adjustment circuit can be constituted by a simple circuit obtained by the terminal resistor 88 having the function of impedance matching and the function of terminating.
The integrated circuit 81 and the integrated circuit 82 are not necessarily mounted on the same substrate or in the same housing. In addition, even though the integrated circuit 81 and the integrated circuit 82 are mounted on the same substrate, voltage drop caused by a pattern resistor may occur because a pattern is drawn on the substrate. For this reason, the potential difference VGAP80 may not be 0 volt. The DC voltage VDC80 and the signal amplitude VAC80 can be expressed by equations (4) and (5), respectively, using the voltage VEE82:                     VDC80        =                ⁢                  VCC82          -                                    (                              I80                xc3x97                RS80                            )                        /            2                    +          VGAP80                                    (        4        )                                                                    VAC80              =                            ⁢                              (                                  VCC82                  -                                      (                                                                  (                                                  VCC82                          -                                                                                    (                                                              I80                                xc3x97                                RS80                                                            )                                                        /                            2                                                                          )                                            +                                                                                                                                                                                                  ⁢                  VGAP80                  )                                )                            xc3x97              2                                                                                                            =                                    ⁢                                                            (                                                                        (                                                      I80                            xc3x97                            RS80                                                    )                                                /                        2                                            )                                        -                    VGAP80                                                  )                            xc3x97              2                                                                          =                            ⁢                                                (                                      I80                    xc3x97                    RS80                                    )                                -                                  2                  ⁢                  VGAP80                                                                                        (        5        )            
According to equation (4), the DC voltage VDC80 across the input terminals 87 and 90 is shifted from a design value at which the internal circuit 89 can be normally operated by volts corresponding to the potential difference VGAP80. According to equation (5), the signal amplitude VAC80 across the input terminals 87 and 90 is shifted from a design value by (xe2x88x922xc3x97VGAP80) volts.
As a conventional self-bias adjustment circuit for avoiding a signal voltage from being shifted by the potential difference VGAP80, a self-bias adjustment circuit in which a capacitor is inserted on a signal line for transmitting an input signal, a signal component passes through the capacitor, and a DC voltage expressed by equation (2) is superposed on the signal component is known. In this self-bias adjustment circuit, the influence of the potential difference VGAP80 is suppressed by the capacitor inserted on the signal line.
However, according to the above-described conventional self-bias adjustment circuit (Design Considerations for Very-High-Speed Si-Bipolar IC""s Operating up to 50 Gb/sxe2x80x3), since the self-bias adjustment circuit has no function of suppressing the influence of the potential difference VGAP80, a shift between a bias voltage and a signal amplitude at the input terminal 90 of the internal circuit 89 is generated, and the internal circuit 89 may not be appropriately operated. In addition, the signal amplitude is disadvantageously deteriorated.
According to the conventional self-bias adjustment circuit having the capacitor, since a capacitor is inserted on a signal line for transmitting an input signal, when the input signal has a frequency component of a wide band, the low-frequency component of the input signal is attenuated, and the input signal is disadvantageously degraded. When the capacitance of the capacitor is set large (e.g., 1 nF or more) to pass the signal components of the wide band, the capacitor increases in size. For this reason, the capacitor is not easily formed in the integrated circuit, and the capacitor must be formed out of the integrated circuit. Therefore, peripheral devices increases in size, and the cost disadvantageously increase.
It is an object of this invention to obtain a self-bias adjustment circuit which can appropriately operate the internal circuit while suppressing the size and cost of the device from being increased and which can reduce a deterioration of a signal amplitude.
In the self-bias adjustment circuit according to the present invention, a detection unit detects the bias voltage of the input signal, and a superposing unit superposes the correction voltage for correcting the bias voltage to the predetermined voltage on the input signal to output the signal to the internal circuit.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.